IEEE Solid-State Circuits Society

IEEE Solid-State Circuits Society Official IEEE Solid-State Circuits Society (SSCS).

With over 10,000 members around the world, SSCS focuses on the needs of professional and student members engaged in the design and fabrication, design and theory, surrounding integrated circuit design.

🚀 Applications are officially OPEN for the first-ever IEEE SSCS / IEEE EDS SEED Program!The Semiconductor Education, Emp...
06/05/2026

🚀 Applications are officially OPEN for the first-ever IEEE SSCS / IEEE EDS SEED Program!

The Semiconductor Education, Empowerment, and Industry Development (SEED) program is a brand-new grassroots outreach initiative designed to bridge the gap in underserved geographic regions with limited educational or industrial exposure to the semiconductor field.

We are selecting four outstanding candidates—two specializing in solid-state circuits and two in electronic devices—to engage directly with local students, faculty, and industry leaders to help build future excellence in microelectronics.

🏆 What’s Included:
• Up to $5,000 USD in grant funding to cover travel, lodging, and report preparation.
• A fully funded, up-to-two-week outreach trip to your chosen underserved region between October and December 2026.

🛠️ Who Should Apply?
Applicants must be current IEEE SSCS or EDS members (use code TRYEDS2026 for free EDS membership!) and fall into one of these categories:

Senior PhD Students (final or penultimate year)

Young Professionals (minimum Master’s degree + 2 years of industry experience)

Junior Faculty (minimum 2 years in an established academic career)

Note: Cultural awareness and local language proficiency for your chosen region are highly preferred to ensure impactful knowledge transfer.

📅 Key Dates:
• Application Portal Closes: August 1, 2026
• Candidate Selection: September 15, 2026
• Program Ex*****on & Travel: Sept 2026 – Jan 2027

Don't miss this unique opportunity to make a lasting global impact, analyze regional infrastructure gaps, and build a strategic roadmap for future SSCS/EDS investments.

Learn more about the required application materials: https://bit.ly/46s1gnT
👉Submit your package here: https://bit.ly/4dVWDXj

📈 Most Cited: Leading JxCDC Articles in 2026 so farThe citation metrics are in, and the hardware engineering community i...
06/04/2026

📈 Most Cited: Leading JxCDC Articles in 2026 so far

The citation metrics are in, and the hardware engineering community is heavily focusing its research on unconventional computing paradigms, advanced magnetic memory devices, and next-generation packaging for AI workloads.

Here are the top three most cited articles from the IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC):

🧠 1. A Full-Stack View of Probabilistic Computing With p-Bits: Devices, Architectures, and Algorithms

* Authors: Shuvro Chowdhury, Andrea Grimaldi, Navid Anjum Aadit, Shaila Niazi, Masoud Mohseni, Shun Kanai, Hideo Ohno, Shunsuke Fukami, Luke Theogarajan, Giovanni Fi*****io, Supriyo Datta, Kerem Y. Camsari

Evaluates how merging emerging nanodevices with the CMOS ecosystem can build energy-efficient probabilistic sampling systems tailored for machine learning, AI, and quantum simulation.
🔗 Read: https://bit.ly/4ba29BH

🧲 2. Review of Magnetic Tunnel Junctions for Stochastic Computing

* Authors: Brandon R. Zink, Yang Lv, Jian-Ping Wang

Provides an in-depth evaluation of the use of magnetic tunnel junctions (MTJs) to implement robust, energy-efficient stochastic computing hardware frameworks.
🔗 Read: https://bit.ly/4u9uT65

📦 3. Heterogeneous Integration Technologies for Artificial Intelligence Applications

* Authors: Madison Manley, Ash*ta Victor, Hyunggyu Park, Ankit Kaul, Mohanalingam Kathaperumal, Muhannad S. Bakir

A comprehensive review of the packaging and heterogeneous integration technologies required to scale system throughput and meet the exponential demands of generative AI workloads.
🔗 Read: https://bit.ly/4lpDY7A

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Which of these highly cited architectural paths is impacting your own research design this year? Let us know your thoughts in the comments below! 👇

🏝️ Networking in Hawaii: Join the WiC & Women in EDS Luncheon at VLSI 2026!Heading to the IEEE Symposium on VLSI Technol...
06/03/2026

🏝️ Networking in Hawaii: Join the WiC & Women in EDS Luncheon at VLSI 2026!

Heading to the IEEE Symposium on VLSI Technology and Circuits? Make sure to secure your seat for one of our most anticipated networking events of the year!

Join the IEEE SSCS Women in Circuits (WiC) and Women in EDS for an afternoon of mentorship, leadership insights, and high-level networking. This luncheon is designed for attendees at all career stages—from students to industry veterans—to exchange perspectives in a relaxed setting.

Featured Speakers:
✨ Dr. Farhana Sheikh (Intel): IEEE Fellow and trailblazer in 3D heterogeneous integration and chiplet research.
✨ Dr. Yue Liang (NVIDIA): Distinguished Engineer leading silicon technology development and foundry management.

📅 Date: Tuesday, June 16, 2026
🕛 Time: 12:00 PM – 2:00 PM
📍 Location: Lehua Suite in Kahili Tower, Hilton Hawaiian Village

⚠️ Registration Note: Separate registration is required, and space is strictly limited. Don't wait—secure your ticket today!

🎟️ Get your tickets here: https://bit.ly/493n8XO

Crisscrossing Switches: The Extreme Physics Inside an EV Power InverterHow do we take a massive, 600V DC battery pack an...
06/03/2026

Crisscrossing Switches: The Extreme Physics Inside an EV Power Inverter

How do we take a massive, 600V DC battery pack and use it to drive a high-performance AC electric motor? The conceptual answer is remarkably simple: you flip the battery terminals back and forth.

But doing that safely at 40A of current without melting the chassis? That is where the real engineering begins.

In Episode 9 of The Beauty of Circuits, Prof. Behzad Razavi deconstructs the architecture of the automotive Power Inverter. He moves from the basic theory of the H-bridge topology to the brutal constraints of real-world solid-state silicon.

Key Engineering Insights:

* The H-Bridge Architecture: How four synchronized transistor switches ($Clk$ and $\overline{Clk}$) dynamically reverse voltage polarity to synthesize an AC waveform from a pure DC source.
* The Tyranny of On-Resistance: Why even a seemingly tiny 1 Ω switch resistance is an absolute catastrophe under a 40A load—resulting in an unacceptable 40V drop and massive thermal waste.
* Real-World Silicon Limits: A look at how commercial components (like Infineon’s power MOSFETs) are engineered to tolerate 750V breakdown thresholds while hammering internal resistance down to an astonishing 60 mΩ.

Power electronics is a game of fractions of an ohm. When you are managing hundreds of volts under heavy acceleration, minimizing efficiency loss isn’t just about saving battery life—it’s about survival of the silicon.

📺 Watch Episode 9: From Cars to Transistors
https://bit.ly/4dRtNFW

Exploratory Breakthroughs: The Most Popular JxCDC Articles in 2026 So Far 📈As conventional scaling changes pace, the har...
06/02/2026

Exploratory Breakthroughs: The Most Popular JxCDC Articles in 2026 So Far 📈

As conventional scaling changes pace, the hardware community is looking toward advanced packaging, backside routing, and unconventional computing paradigms to drive performance forward.

Here are the three IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC) articles that have gathered the most attention so far this year:

📦 1. 3-D Stacked HBM and Compute Accelerators for LLM: Optimizing Thermal Management and Power Delivery Efficiency
Janak Sharda, Madison Manley, Jungyoun Kwak, Chinsung Park, Muhannad Bakir, Shimeng Yu
• Explores design configurations like logic-on-memory, memory-on-logic, and hybrid systems for Large Language Model hardware accelerators. Proposes mitigation strategies that reduce IR drop by 640 mV and deliver up to 4× higher throughput compared to conventional 2.5-D integrated systems.
🔗 Read: https://bit.ly/4dcP8ey

🔌 2. Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard-Cell Scaling
Anup Ashok Kedilaya, Sirish Oruganti, Nishant Gupta, Xiuhao Zhang, Ilya Karpov, Mark A. Anders, Jaydeep P. Kulkarni
• Investigates using backside contact technology to extend signal and clock routing in sub-3-nm technologies. Cell height reduction delivers up to 35% area savings, up to 15% power reduction, and a 32% lower worst-case IR drop compared to standard backside power delivery.
🔗 Read: https://bit.ly/4dKqlOQ

🧠 3. A Full-Stack View of Probabilistic Computing With p-Bits: Devices, Architectures, and Algorithms
Shuvro Chowdhury, Andrea Grimaldi, Navid Anjum Aadit, Shaila Niazi, Masoud Mohseni, Shun Kanai, Hideo Ohno, Shunsuke Fukami, Luke Theogarajan, Giovanni Fi*****io, Supriyo Datta, and Kerem Y. Camsari
• Provides a full-stack review of energy-efficient, domain-specific probabilistic computing using p-bits. Outlines key hardware, architecture, and algorithmic applications ranging from machine learning and AI to combinatorial optimization and quantum simulation.
🔗 Read: https://bit.ly/4ba29BH

Which of these exploratory architectures is driving your research forward? Drop your thoughts in the comments!

🌴 Heading to Hawaii for VLSI 2026? Accelerate your career or give back to the engineering community at the upcoming Youn...
06/01/2026

🌴 Heading to Hawaii for VLSI 2026? Accelerate your career or give back to the engineering community at the upcoming Young Professionals Mentoring and Networking Event!

Co-hosted by the IEEE Solid-State Circuits Society (SSCS) and Electron Devices Society (EDS), this event is the perfect opportunity for students and early-career professionals to connect with industry leaders—and for experienced attendees to help shape the next generation of engineers.

Why attend?
💡 Gain insights from leading industry experts and professors.
🙋‍♂️ Ask career questions in a relaxed, welcoming environment.
🤝 Connect with fellow young professionals and students from around the globe.
🍕 Enjoy complimentary refreshments!

🙌 Call for Mentors: If you are attending VLSI 2026 in person, please consider being a mentor to share your insights and experiences. Sign up to mentor here: https://app.smartsheet.com/b/form/019e4d8e09ae748f8790bb926626340d

Event Details:
📅 Time: Tuesday, June 16 | 6:00 PM - 7:30 PM
📍 Location: Lehua Suite (2nd Floor, Kalia Tower in the Kalia Executive Conference Center of the Hilton Hawaiian Village)

We look forward to seeing you there!

🌐 Stay connected with the IEEE Solid-State Circuits Society!Follow us across all platforms to stay up to date on the lat...
05/30/2026

🌐 Stay connected with the IEEE Solid-State Circuits Society!

Follow us across all platforms to stay up to date on the latest SSCS conferences, webinars, publications, and community initiatives.
Get inspired by the engineers driving innovation in solid-state circuits around the world.

📲 Follow us on:
🔗 LinkedIn - https://lnkd.in/eQ3VANtT
🔗X (Twitter) - x.com/SSCSociety
🔗Instagram - instagram.com/ieeesscs
🔗Facebook - https://lnkd.in/et7f8m3M
🔗YouTube - https://lnkd.in/ehDE2XRK
🔗Bluesky - https://lnkd.in/eYrbtYNy

Join the conversation — engage, share, and help us advance technology for humanity.

🚀 Final Countdown: The 2026 IEEE SSCS Student Circuit Contest Deadline is Approaching! ⏳Undergraduate and graduate stude...
05/29/2026

🚀 Final Countdown: The 2026 IEEE SSCS Student Circuit Contest Deadline is Approaching! ⏳

Undergraduate and graduate student designers—this is your last weekend to prove your IC design skills on a global stage. The IEEE Solid-State Circuits Society (SSCS) Student Circuit Contest officially closes this Sunday!

This isn't your typical design project. The challenge? Build a functional integrated circuit using only a restricted list of components. It’s a game of optimization, creativity, and "doing more with less."

🏆 The Stakes
• Up to 3 Winners: Receive US$2,000 toward attending a premier SSCS-sponsored conference (ISSCC, CICC, ESSCIRC, VLSI Symposium, or A-SSCC).
• All Sound Submissions: Get one year of free membership in the IEEE Solid-State Circuits Society!

🛠️ The Challenge
• Constraint: You must use the provided list of NMOS, PMOS, and passive components.
• Goal: Maximize the number of components used while ensuring proper functionality (amplifiers must amplify, oscillators must oscillate!).
• Tech: Use any IC technology available to you (must have both NMOS and PMOS).
• Format: A concise 2-page IEEE-style paper including analysis and simulation results.

📅 Key Details
• Deadline: May 31, 2026 (Any time zone—less than 72 hours remaining!)
• Eligibility: Open to individuals or teams of two. Must be an IEEE member.

Finish up those simulations, finalize your 2-page paper, and get your work in front of the SSCS evaluation committee before the clock runs out!

👉 Check the full rules and component list here: https://bit.ly/4jVCLTM
🔗 Upload your answer and fill out the submission form: https://bit.ly/40oNIG4

Leading the Field: The Most Cited JSSC Papers in 2026 So Far 📈Certain breakthroughs lay such a strong foundational bluep...
05/28/2026

Leading the Field: The Most Cited JSSC Papers in 2026 So Far 📈

Certain breakthroughs lay such a strong foundational blueprint that they continue to anchor the field decades later. Here are the three IEEE Journal of Solid-State Circuits (JSSC) articles that have accumulated the highest number of citations so far in 2026:

🖥️ Design of an image edge detection filter using the Sobel operator
• Authors: Nick Kanopoulos, Nagesh Vasanthavada, and Robert L. Baker
• Summary: Presents a highly pipelined 2-μm CMOS chip architecture designed to operate with a 10-MHz clock. It performs roughly 200 million additions/s to compute gradient magnitude and direction for real-time image edge detection, validated by a working prototype system.
🔗 Read the full paper: https://bit.ly/4r4yBN8

👁️ A 128×128 120 dB 15 μs Latency Asynchronous Temporal Contrast Vision Sensor
• Authors: Patrick Lichtsteiner, Christoph Posch, and Tobi Delbruck
• Summary: Details a 128x128 pixel CMOS vision sensor built in a 0.35-μm process. By combining a logarithmic photoreceptor with a switched-capacitor differencing circuit, the sensor independently tracks relative intensity changes in continuous time, achieving a 120 dB dynamic range, 23 mW power consumption, and 15 μs minimum latency.
🔗 Read the full paper: https://bit.ly/4r8nT8B

📐 Design of ion-implanted MOSFET's with very small physical dimensions
• Authors: Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu, V. Leo Rideout, Ernest Bassous, and Andre R. LeBlanc
• Summary: Establishes the fundamental scaling relationships for reducing conventional MOSFETs to 1-μm dimensions. It introduces an improved structure using ion implantation to provide shallow junctions and nonuniform substrate doping, successfully verified by fabricating polysilicon-gate devices down to 0.5-μm channel lengths.
🔗 Read the full paper: https://bit.ly/4wWtVNi

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Which of these fields is driving your research forward? Drop your thoughts in the comments below! 👇

From Vital Signs to Diodes: The Micro-Seconds Behind Your PulseHow does a lightweight wearable device monitor your heart...
05/27/2026

From Vital Signs to Diodes: The Micro-Seconds Behind Your Pulse

How does a lightweight wearable device monitor your heart rate and blood pressure non-invasively, without losing a single beat of accuracy? It isn't a simple timer—it's high-speed analog processing.

In Episode 8 of The Beauty of Circuits, Prof. Behzad Razavi breaks down the architecture of optical health tracking (Photoplethysmography). He deconstructs how engineers turn a stream of photons passing through a human finger into a highly precise digital medical reading.

Key Engineering Insights:

The Electro-Optical Interface: Passing LED light through blood vessels to measure varying absorption rates as the heart contracts and relaxes.

The Photo-Current Conversion: Operating a photodiode in reverse bias to turn incoming photons into free-moving electron-hole pairs.

The 0.4-Millisecond Window: Why a 1-second heartbeat must be sampled every 0.4 milliseconds to accurately map critical systolic and diastolic peaks.

Data Protection: Utilizing a high-impedance MOSFET source follower to buffer the capacitor's voltage without corrupting the delicate charge data.

📺 Watch Episode 8: From Vital Signs to Diodes
https://bit.ly/4uzfTPW

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