IEEE Solid-State Circuits Society

IEEE Solid-State Circuits Society Official IEEE Solid-State Circuits Society (SSCS).

With over 10,000 members around the world, SSCS focuses on the needs of professional and student members engaged in the design and fabrication, design and theory, surrounding integrated circuit design.

📢 Trending in OJ-SSCS: Most Cited Articles of 2026 Thus Far!The IEEE Open Journal of the Solid-State Circuits Society (O...
06/18/2026

📢 Trending in OJ-SSCS: Most Cited Articles of 2026 Thus Far!

The IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) continues to drive immediate global impact. These three papers have emerged as the most-cited research papers so far this year, shaping the future of AI hardware, next-gen wireless networks, and power management.

Which one is on your reading list?

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1. High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions
Authors: Shenggao Li, Mu-Shan Lin, Wei-Chih Chen, Chien-Chun Tsai
The Core: As AI/ML exponentially demands more computing performance, 2.5D and 3D chiplet integration is vital. This widely cited article addresses the crucial co-optimization of bandwidth density, energy efficiency, electromigration, and signal/power integrity using simpler parallel data buses and forwarded clocks.
Read the open-access paper: https://bit.ly/4jpEwIP

2. Terahertz Integrated Circuits and Systems for High-Speed Wireless Communications: Challenges and Design Perspectives
Author: Payam Heydari
The Core: Looking past 5G toward sub-THz and THz systems (100 GHz to 10 THz) for multi-gigabit wireless? This foundational paper lays bare the exact limits of conventional transceivers and explores pathways to address challenges in front-end amplifiers, LO generation, and antenna arrays.
Read the open-access paper: https://bit.ly/4acCFmG

3. An Overview of Hybrid DC–DC Converters: From Seeds to Leaves
Authors: Yan Lu, Junwei Huang, Zhiguo Tong, Tingxu Hu, Wen-Liang Zeng, Mo Huang, Xiangyu Mao, Guigang Cai
The Core: Delivering sub-1 V rails from high-voltage buses to modern processors poses severe power-delivery challenges. This brilliant review charts the evolution of switched-capacitor-inductor (SCI) hybrid buck topologies across 6 distinct seeds, providing circuit designers with intuitive rules of thumb.
Read the open-access paper: https://bit.ly/3JXktSB

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Why publish in OJ-SSCS?
As a fully open-access journal, your work gets immediate global visibility, leading to faster citations, wider reach, and rapid peer review.

⚡ Where Filtering Meets Analog-to-Digital Conversion: Join the IEEE SSCS June Technical Webinar!System design is often a...
06/17/2026

⚡ Where Filtering Meets Analog-to-Digital Conversion: Join the IEEE SSCS June Technical Webinar!

System design is often a balancing act, especially when trying to simplify things while maintaining inherent anti-alias filtering without sacrificing power or linearity. The Continuous-Time Pipelined (CTP) ADC architecture offers a fundamental improvement over the conventional active filter-ADC cascade—delivering better power efficiency and superior linearity.

In this upcoming technical tutorial, we will trace the evolution of the CTP ADC from first principles, break down the limitations of a standalone filter+ADC chain, and build up the CTP concept stage by stage. We will also explore the extension of CTP principles to bandpass signal processing—where the power-noise product actually improves with increasing filter Q. Concepts will be validated using real silicon results from prototype chips in 65 nm CMOS.

🎙️ Featured Speaker:
Dr. Shanthi Pavan
NT Alexander Institute-Chair Professor of Electrical Engineering at the Indian Institute of Technology Madras, IEEE Fellow, and co-author of "Understanding Delta-Sigma Data Converters".

📅 Date: Monday, June 29, 2026
🕘 Time: 9:00 AM – 11:00 AM EDT
📍 Location: Online (Webex)
🔗 Registration Link: https://bit.ly/4vNkSwF

Whether you are looking to optimize high-speed analog circuit design or deepen your knowledge of continuous-time data converters, this session will provide deep technical insights from an industry pioneer.

Secure your spot and register today!

The Inductive Threat: Protecting Silicon Switches From Infinite VoltageWhen a digital microcontroller commands a robotic...
06/17/2026

The Inductive Threat: Protecting Silicon Switches From Infinite Voltage

When a digital microcontroller commands a robotic arm to halt mid-motion, it sends a simple 0 to its digital-to-analog converter. But down at the physical circuit layer, that simple command triggers a massive inductive crisis.

In Episode 11 of The Beauty of Circuits, Prof. Behzad Razavi details how engineers safely translate digital binary bits into smooth analog motor currents while neutralizing one of the most destructive phenomena in power design: inductive kickback.

# # # Key Engineering Insights:

* Binary-Weighted Scaling: How a multi-branch MOSFET array scales currents geometrically (I0, 2I0, 4I0) to yield 8 precise, predictable analog current levels for motor velocity.
* The Math of Sudden Halts: Why forcing an inductive load (like motor windings) to stop conducting instantly drops the current derivative toward negative infinity.
* The Clamping Solution: Utilizing a classic flyback diode loop to redirect trapped magnetic energy safely into the rail line, capping voltage spikes before they compromise the delicate MOSFET drain terminals.

Great system design isn't just about constructing efficient pathways for data; it's about anticipating exactly where high-energy transients will bottleneck when that data path shuts down.

📺 Watch Episode 11: From Robots to Current Sources
https://bit.ly/4a2hx4x

📢 **Deadline Extended to June 24, 2026!** 📡 Call for Papers: High-Performance Fractional-N PLLs – OJ-SSCS Special Sectio...
06/16/2026

📢 **Deadline Extended to June 24, 2026!**
📡 Call for Papers: High-Performance Fractional-N PLLs – OJ-SSCS Special Section

You now have two extra weeks to submit your manuscript! The IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) has extended the submission window for the Special Section on High-Performance Fractional-N Phase-Locked Loops.

As 5G/6G wireless transceivers and AI clusters drive the demand for ultra-low-jitter clocking, deep sub-picosecond RMS jitter and high spectral purity are more critical than ever. Submit your original research or survey papers addressing modern frequency synthesis.

Topics of Interest Include:

* Architectures: Low-jitter analog, digital, and hybrid PLLs; sampling-based and bang-bang phase detection.
* Agile Synthesis: High-linearity FMCW modulation and fast-settling synthesizers for radar and sensing.
* Applications: 200+ Gb/s wireline clocking, automotive radar, and sub-THz generation.
* Digital Assistance: ML-enhanced calibration for jitter, spur, and modulation optimization.
* Building Blocks: Ultra-low-noise oscillators, high-resolution TDCs, and DTCs.

Why Publish in OJ-SSCS?

* Open Access: Immediate global visibility for your research.
* Rapid Timeline: Fast peer-review and swift decision times.

📅 Updated Key Dates:

* Submission Deadline: June 24, 2026 (Extended!)
* First Notification: July 17, 2026
* Final Decision: September 14, 2026
* Publication Online: September 25, 2026

Guest Editors: Dr. Teerachot Siriburanon (UCD) and Dr. Ping Lu (NVIDIA).

🔗 Submit Your Manuscript via Manuscript Central: https://bit.ly/4qP5DBV
(Select “High-Performance Phase-Locked Loops” during submission)

Find more information on the official page: https://bit.ly/4sianiY

Are you attending VLSI 2026 right now? The IEEE Solid-State Circuits Society (SSCS) has an incredible lineup of events u...
06/15/2026

Are you attending VLSI 2026 right now? The IEEE Solid-State Circuits Society (SSCS) has an incredible lineup of events underway at the Hilton Hawaiian Village to help you network, learn, and excel! Make sure these are on your schedule for this week:

🗓️ Tuesday, June 16 (Happening Tomorrow)

* 👥 WiC & Women in EDS Networking Luncheon
* Time: 12:00 PM – 2:00 PM HST | Room: Lehua Suite (Kahili Tower)
* Connect with peers across academia and industry in a relaxed setting. This session features brief, insightful remarks from guest speakers Dr. Farhana Sheikh (Principal Engineer & Manager, Intel Corporation and newly elevated IEEE Fellow) and Dr. Yue Liang (Distinguished Engineer, NVIDIA Corporation). Space is limited, so early registration is highly recommended!

👉 Register here: https://bit.ly/4okRE62

* 🤝 YP & EDS Mentoring and Networking Event
* Time: 6:00 PM – 7:30 PM HST | Room: Hilton Hawaiian Village
* Designed for students and young professionals to bridge the gap between academic study and industry leadership. Sit down with leading experts, executives, and professors to ask honest questions about navigating the job market, research, and engineering trends. Complimentary refreshments are being served!
* Call for Mentors: If you are an experienced professional, senior researcher, or faculty member, please consider volunteering your time to help shape the next generation!

👉 Sign up as a mentor here: https://bit.ly/4uHJuXw

* 🎙️ YP Distinguished Lecturer Preview
* Time: 7:30 PM - 9:00 PM HST | Room: Kahili Suite (2nd Floor, Kalia Tower)
* Join SSCS YP and the IEEE Hawaii Jt. SSCS/EDS Chapter for condensed, high-quality presentations from widely recognized experts on the SSCS Distinguished Lecturer roster. Don’t miss this chance to see highly polished talks and bring a DL back to your local chapter!

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🧸 Need Childcare? SSCS Has You Covered!

To give you complete peace of mind while you attend technical sessions, the SSCS Children’s Program through KiddieCorp is running right now! While online pre-registration is now closed, **on-site registration is fully open**. Simply drop by to register your child!

* Dates: June 15-18, 2026 (Running Now!) | Room: Hibiscus Suite
* Who: Open for children ages 6 months through 12 years old.
* Cost: Only $5.00/hour per child for SSCS members ($10.00/hour for non-members).
* Please Note: VLSI does not allow children in the conference sessions or lobby spaces, so separate on-site registration is required.

We are so excited to see everyone here in Hawaii for an inspiring week of connection and community! 🌺
Click the link in our comments to purchase luncheon tickets or sign up as a mentor!

Momentum is Building: The SSCS INSPIRE Program is Expanding! 🚀After its successful debut in 2024 and a landmark first fu...
06/13/2026

Momentum is Building: The SSCS INSPIRE Program is Expanding! 🚀

After its successful debut in 2024 and a landmark first full year in 2025, the IEEE Solid-State Circuits Society (SSCS) is thrilled to announce the 2026 expansion of the INSPIRE Program (Inspiring New Students to Pursue Integrated Circuits Regional Education)!

The INSPIRE Program empowers SSCS Chapters to lead local outreach that introduces young students to the world of integrated circuits. Having proven the model over the last two years, we are now expanding our reach to help even more chapters bridge the gap between today’s experts and tomorrow’s engineers.

💡 Why your Chapter should apply for Year 3:

- Proven Impact: Join a growing global movement of chapters bringing STEM education to life.
- Funding Available: Approved proposals can receive up to $1,500 USD to support hands-on PCB workshops, high school seminars, or teacher training.
- Global Expansion: We are looking to fund a more diverse range of outreach activities than ever before.

🗓️ 2026 Key Dates:

Submission Deadline: June 30, 2026
Activity Completion: By October 31, 2026
Note: Funding is first-come, first-served. Submit your proposal early!

Let’s build on the foundation we've laid since 2024 and make 2026 our most impactful year yet for global IC outreach.

🔗 Learn more & submit your proposal: https://lnkd.in/eb_iqcjj

🏆 Nominations are officially open for the IEEE Solid-State Circuits Society (SSCS) Awards! From now through October 15, ...
06/12/2026

🏆 Nominations are officially open for the IEEE Solid-State Circuits Society (SSCS) Awards! From now through October 15, recognize the innovators, educators, and leaders shaping the future of integrated circuits.

Submit your nomination packages directly through the updated platform links below:

🎨 IEEE Brokaw Award for Circuit Elegance
Celebrates smart, simple, and elegant small-circuit designs created over the last decade.
🔗 Submit: https://bit.ly/44uRfpI

🚀 New Frontier Award
Honors early-career members pushing the boundaries of circuit technologies, system design, or emerging applications.
🔗 Submit: https://bit.ly/4ouJAz6

🏢 Industry Impact Award
Celebrates technical breakthroughs, leadership, or entrepreneurship that created major paradigm shifts in the IC business.
🔗 Submit: https://bit.ly/4121eAn

🎓 Innovative Education Award
Recognizes educators using creative, impactful approaches to inspire the next generation of IC designers.
🔗 Submit: https://bit.ly/45o044t

💡 James D. Meindl Innovators Award
Supports highly creative projects and development grants that build excitement around the IC field.
🔗 Submit: https://bit.ly/44UWDlS

🤝 Distinguished Service Award
Honors members demonstrating exceptional leadership and sustained commitment to the Society's global mission.
🔗 Submit: https://bit.ly/46wNdOv

🎓 SSCS Predoctoral Achievement Award
Recognizes outstanding PhD students in the field of solid-state circuits.
🔗 Submit: https://bit.ly/4e2xuKz

📅 Deadline: October 15, 2026, at 11:59 PM ET.

Don't let exceptional contributions go unnoticed. Elevate your peers, mentors, and students today!

📡 Call for Papers: IEEE OJ-SSCS Special Section on Low Power Wireless TransceiversFrom the Internet of Things (IoT) and ...
06/11/2026

📡 Call for Papers: IEEE OJ-SSCS Special Section on Low Power Wireless Transceivers

From the Internet of Things (IoT) and body area networks to high-accuracy localization and implantable biomedical devices, minimizing power consumption is critical for next-generation wireless systems.

The IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) is officially inviting submissions for an upcoming Special Section dedicated to the latest breakthroughs in low-power radios, blocker-tolerant circuits, and energy-harvesting solutions.

We are seeking both original research articles featuring silicon-verified prototypes and in-depth review papers highlighting state-of-the-art techniques.

📌 Topics of Interest include (but are not limited to):
• Low-power transceivers for localization, tracking, and ranging
• Integrated sensors and systems for biomedical and IoT applications
• Low-power, blocker-resilient circuits and blocks compliant with BLE 5.x, UWB, and NB-IoT
• Energy harvesting and power management for implantable/wearable devices
• Wirelessly powered battery-free radios and backscatter WiFi

📅 Important Dates:
• Submissions Open: June 10, 2026
• Submission Deadline: August 10, 2026
• Final Decision: October 26, 2026
• Publication Online: November 10, 2026

Guest Editors:
• Prof. Mustafijur Rahman (IIT Delhi)
• Prof. Hamed Rahmani (New York University)

👉 Learn more about formatting requirements and submit your manuscript here: https://bit.ly/4qP5DBV (Be sure to select “Low Power Wireless Transceivers” upon submission.)

When Silicon Meets Steel: The Op-Amp Math Behind a Robot’s TouchHow do you train a heavy, high-speed industrial robot to...
06/10/2026

When Silicon Meets Steel: The Op-Amp Math Behind a Robot’s Touch

How do you train a heavy, high-speed industrial robot to pick up a fragile egg without crushing it or dropping it? You don’t just write better software—you optimize the analog front-end.

In Episode 10 of The Beauty of Circuits, Prof. Behzad Razavi takes us inside the control loop of a modern robotic arm. He demonstrates how a classic Wheatstone bridge-operational amplifier combination scales microscopic pressure changes into crisp motor commands.

Key Engineering Insights:

* The DC Offset Problem: Why reading a tiny 50 mV sensor shift on top of a heavy 1V DC bias level is an error-prone nightmare, and how a differential bridge circuit eliminates the offset.
* Differential Gain Trajectory: Modifying the bridge architecture to use dual sensors, driving node $V_X$ down while pushing node $V_Y$ up to double the sensitivity under the same physical load.
* The Critical Damping Threshold: Translating mechanical motion into system dynamics. We analyze why an underdamped loop produces wild oscillations that can break the payload, and why achieving a critically damped state is the gold standard for speed and safety.

Whether you design sensor networks or industrial automated systems, understanding the mathematical settling behavior of your feedback loops is what separates an efficient line from a broken product.

📺 Watch Episode 10: From Robots to Op Amps
https://www.youtube.com/watch?v=hctPCfr1sHY

🚀 The top 3 most popular papers in the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) so far in 2026 hi...
06/09/2026

🚀 The top 3 most popular papers in the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) so far in 2026 highlight breakthrough research shaping next-generation computing hardware. From AI/ML chiplet integration to ultra-fast transceivers, here is what the global IC community is reading right now:

1️⃣ High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions
💡 Authors: Shenggao Li, Mu-Shan Lin, Wei-Chih Chen, Chien-Chun Tsai
🔬 What it covers: As AI/ML demand skyrockets, this paper breaks down the critical 2.5D and 3D design roadblocks—including bandwidth density, signal integrity, and electromigration—and explores the power of modern 3D-IC design co-optimization.
🔗 Read on IEEE Xplore: https://bit.ly/4jpEwIP

2️⃣ An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier
💡 Authors: Lu Jie, Xiyuan Tang, Jiaxin Liu, Linxiao Shen, Shaolan Li, Nan Sun, Michael P. Flynn
🔬 What it covers: The definitive guide to the rise of the Noise-Shaping (NS) SAR ADC. It traces how combining SAR and DSM architectures maximizes process-scaling efficiency while providing in-depth analysis of loop filtering, DAC mismatch mitigation, and bandwidth boosting.
🔗 Read on IEEE Xplore: https://bit.ly/4acNTYa

3️⃣ Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications
💡 Authors: Ahmad Khairi, Amir Laufer, Ilia Radashkevich, Yoel Krupnik, Jihwan Kim, Tali Warshavsky Grafi, Ajay Balankutty, Yaniv Sabag, Yoav Segal, Udi Virobnik, Mike Peng Li, Itamar Levin, Yosef Ben Ezra, Ariel Cohen
🔬 What it covers: Real silicon results from an advanced 3-nm CMOS transceiver pulling off 224 Gb/s data rates. This proof of concept is paving the way for ultra-low-latency, power-efficient optical communication in high-performance computing (HPC) networks.
🔗 Read on IEEE Xplore: https://bit.ly/4etJJjj

Which of these hardware breakthroughs are you implementing in your own design pipelines? Let’s discuss in the comments below!👇

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